Home › Forums › Design and Building › Effects Design and Construction › Signaltap Effects Design Operation!

Viewing 1 post (of 1 total)
  • Author
    Posts
  • November 8, 2017 at 8:15 am #7953
    Joe
    Participant

    I am working on a design in Verilog. The design works normally with signaltap enabled. But, when I disable signaltap, the operation of the circuit changes. The results become erroneous. I think signaltap is an observer only, so it shouldn’t change the design operation. Does anyone have an idea about this problem?

    I didn’t find the right solution from the internet.

    References:
    https://www.alteraforum.com/forum/showthread.php?t=2405987456

    advertisement examples

  • Author
    Posts
Viewing 1 post (of 1 total)
  • You must be logged in to reply to this topic.